1. Field of the Invention
The present invention relates to a signal connection system for a relatively large semiconductor chip. This invention is to some extent related to an invention described in application Ser. No. 590,651 filed Mar. 19, 1984, and application Ser. No. 590,677 filed Mar. 19, 1984, which is assigned to the assignee of the present invention.
2. Description of the Prior Art
Semiconductor die or "chips" are normally formed in multiples in a silicon wafer, on the order of 5 inches in diameter. The wafer is then cut into individual chips, usually no larger than about 50 square millimeters, which contain a large number of electronic circuit elements. Logic chips which perform arithmetic computation functions, for example the function of addition, are now in production which have more than 40,000 transistors and other circuit elements in a 50 square millimeter area.
One limitation on the size of the chip has been the fact that electrical connections must be made between the various circuits on the chip and other circuits in the system. Typically, chips are rectangular with contacts along their two long edges, or square with contacts along their two long edges, or square with contacts along all four sides, to which the necessary external electrical connections are made. As the size of the chip increases, the number of circuits which can be located on the chip increases much more rapidly than the number of contacts available on its periphery. Attempts have been made to provide a two dimensional array of contacts on one face of the chip, but the difficulty of making pin-point soldered connections between the flat surface of the chip and the flat substrate is itself a limitation on the size of the chip. The number of logic circuits which can be accommodated on a single chip is thus limited by the necessity of connecting the circuits to other system elements, and the chips themselves have been quite small.